Computing

IBM claims world’s first sub-1 nanometer chip technology

techexpresshub Staff25 June 2026 at 10:00 UTC1 min read
IBM claims world’s first sub-1 nanometer chip technology

To overcome the physical scaling limits facing modern chip designers, IBM’s new nanostack architecture vertically stacks transistors in a staggered layout to pack more transistors into the same chip space. The nanostack architecture builds on the company’s prior development of nanosheet transistors that paved the way for its 2-nanometer chip node introduced in 2021.

The basic unit of IBM’s nanostack architecture consists of two transistors stacked and bonded together. Each transistor consists of three nanosheets that are individually 5 nanometers thick, equivalent to about 15 rows of silicon atoms. There is also a distance of about 9 nanometers separating each nanosheet.

Performance gains for the AI era

The nanostack architecture could pave the way for 50 percent higher computing performance or 70 percent greater energy efficiency than IBM’s previous generation of 2-nanometer node chips, according to projections from the company’s published technical reports. The company introduced its nanostack transistor architecture at the 2025 IEEE Symposium on VLSI Technology and Circuits held in Kyoto, Japan.

IBM researchers also showed how the nanostack architecture can provide 40 percent improvement in scaling for static random-access memory (SRAM) during the VLSI 2026 symposium. SRAM allows for fast but energy-intensive read and write operations that are crucial in many AI applications.

The memory improvement is made possible through a staggered-channel design for the chip’s SRAM bit cells—memory storage units consisting of six transistors—that reduces overall cell height by 40 percent and enables more SRAM to be squeezed into the same chip space.

That will probably be welcome news for chip designers looking to support AI workloads, given how SRAM scaling has fallen off drastically in recent generations of chip technologies. For example, SRAM scaling improved just a few percent between the 3-nanometer chip generation and the 2-nanometer chip generation, Gambetta explained.

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